Wed 15 Jul 2026 / 19:44 ET
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Hardware 3 min read

Nvidia says Vera Rubin is in production as rack-delay reports linger

Jensen Huang rejected broad delay claims, while Nvidia gave a narrower answer on reported trouble with its 144-GPU Rubin Ultra rack.

Felix Aranda

By Felix Aranda / Silicon Editor

Nvidia says Vera Rubin is in production as rack-delay reports linger
img: Tom's Hardware

Nvidia chief executive Jensen Huang told reporters in Japan that the company’s Vera Rubin AI platform is already being built, pushing back on talk that the next-generation hardware has slipped. The denial matters because Nvidia’s largest customers buy these systems on long planning cycles, and a delay in the wrong rack design can ripple through data-center power, cooling and procurement plans.

Huang told Bloomberg that reports of Vera Rubin delays were “not true,” adding that Vera Rubin is in production and that “giant amounts” are coming. Nvidia had already said earlier this year that Vera Rubin production had begun in January, and Tom’s Hardware reported customer sampling in February.

That answers one question: Nvidia says the core Vera Rubin platform is moving. It does not settle the more specific claim that a larger Rubin Ultra rack-scale system, known as Kyber NVL144, has slipped.

SemiAnalysis reported earlier this month that Kyber NVL144, a design intended to connect 144 Rubin Ultra GPUs, has moved by more than a year from 2027 into 2028. Nvidia did not give Tom’s Hardware a point-by-point denial of that report. A company spokesperson instead said, “Our roadmap is intact.”

That wording is doing a lot of work. It says Nvidia still expects to offer products on its public plan. It does not say every configuration remains on its earlier schedule, nor does it confirm SemiAnalysis’ timeline.

The hard part is the rack, not just the GPU

The reported problem centers on Kyber’s copper-based NVLink 7 scale-up fabric. In plain terms, Nvidia wanted a 144-GPU machine in which the accelerators could talk to one another over high-speed electrical links as one large low-latency domain. To do that, SemiAnalysis said, the system depended on a complex printed circuit board midplane connecting major parts of the rack.

SemiAnalysis did not claim that defective Rubin Ultra chips caused the delay. Its report pointed instead to manufacturability of the PCB infrastructure. That distinction matters. A GPU can be good silicon and still be trapped inside a rack design that is miserable to manufacture at volume. The data-center business has no patience for a beautiful topology that cannot be built reliably.

SemiAnalysis also reported that Nvidia considered an alternative copper design called NVL72x2, which would have placed two Oberon racks back-to-back to enlarge the NVLink domain without optical interconnects. According to the firm, customers rejected that setup and its operational requirements. The report did not name those customer objections, though Tom’s Hardware noted they could involve serviceability, cooling, cabling or data-center layout.

A larger NVL576 design, reportedly based on eight Oberon racks linked with co-packaged optics between NVSwitches, has also been postponed or limited in volume because of continuing CPO challenges, SemiAnalysis claimed. The existence of that plan suggests Nvidia has been developing optical switch-to-switch links for Rubin-generation systems, but available reporting does not show whether that technology could replace Kyber’s copper midplane with the same topology, bandwidth and latency.

The rack reports follow another SemiAnalysis claim that Nvidia canceled a quad-compute-chiplet Rubin Ultra GPU design in favor of a dual-compute-chiplet version projected to deliver half the performance. If the Kyber and NVL72x2 reports hold, Tom’s Hardware noted that Nvidia would be limited to 72-way scale-up systems until sometime in 2028.

That could give rivals more room in large accelerator domains. Tom’s Hardware cited AMD’s planned Mega Pod, based on Verano CPUs and Instinct MI500-series accelerators, as expected to include up to 256 accelerators. It also cited Google’s TPU 8i as offering roughly 1,024 to 1,152 accelerators within one low-latency domain, while TPU 8t can reach 9,600 chip packages per domain.

This story draws on original reporting from Tom's Hardware.

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