AMD’s Instinct MI455X CDNA 5 accelerator is built for a 72-GPU Helios rack rather than the familiar standalone-server pitch. That is the consequential change: AMD is selling a chip, certainly, but the intended unit of deployment is a liquid-cooled rack whose accelerators can exchange data directly at high bandwidth. AMD positions the system for large-model training, fine-tuning and inference. The company has not supplied pricing, broad availability timing, power figures or independent benchmark results.
The MI455X is the first product AMD has introduced using its fifth-generation CDNA compute architecture, according to the company. CDNA is AMD’s dedicated architecture for Instinct accelerators, designed around high-bandwidth memory, chiplets and matrix math for AI and high-performance computing.
What changes with AMD Instinct MI455X CDNA 5?
The physical layout divides the job among specialized silicon. AMD specifies eight compute chiplets containing 256 Work Group Processors, two fabric-and-cache dies, and two I/O dies. The fabric-and-cache dies hold 192 MB of global L2 cache; the I/O dies connect the device to host and networking interfaces. AMD says this partitioning lets it optimize compute, cache, memory and I/O separately.
AMD says the design uses 3D hybrid-bonded compute dies and Infinity Fabric for on-package communication. Itdaily reports that the package uses CoWoS-L packaging and 3D hybrid bonding.
On the execution side, CDNA 5 moves to native Wave32 execution. AMD says that change improves SIMD utilization and reduces synchronization overhead. Itdaily reports that the prior Wave64 approach has been replaced, with the new design intended to lower instruction latency and reduce branching penalties. CDNA 5 also supports MXFP8, MXFP6 and MXFP4 low-precision formats with block scaling and fractional scaling, according to AMD.
MI455X specifications at a glance
- 432 GB of HBM4 memory across 12 stacks
- Up to 23.3 TB/s of peak theoretical memory bandwidth
- 192 MB of global L2 cache
- Eight compute chiplets and 256 Work Group Processors
- 2 nm and 3 nm process technologies in the CDNA 5 design
- 3.6 TB/s of bidirectional scale-up bandwidth per GPU for Helios
AMD’s generation table lists CDNA 4 at up to 185 billion transistors, HBM3E memory and 8 TB/s of peak bandwidth. CDNA 5 is listed at up to 320 billion transistors, HBM4 and 23.3 TB/s. Those are architectural specifications, not proof of application-level performance.
Why does Helios use 72 MI455X GPUs?
Helios makes the rack the system boundary. AMD says its UALoE fabric gives the 72 GPUs all-to-all, single-hop communications within a shared memory pod. The per-device and rack figures need keeping separate: 72 accelerators with 432 GB each equal 31,104 GB, matching AMD’s rounded 31 TB rack-memory figure. Likewise, 72 times 3.6 TB/s equals 259.2 TB/s, which explains the roughly 260 TB/s rack-level scale-up figure.
Software remains part of the wager. AMD says its ROCm stack provides distributed execution, RCCL communication primitives, KV-cache optimizations, and overlap between computation and communication for Helios. AMD also makes performance and competitive claims for the platform, including comparisons with Nvidia systems, but the material available does not include independent tests that establish those claims.
This story draws on original reporting from ServeTheHome.
