A Google TPU 2028 buildout could put the company at or above Nvidia’s annual data center AI accelerator shipments, according to a Fubon Research note circulated by Sean on X. Fubon said its checks indicate Google plans to have 12 million to 15 million ninth-generation TPUs in 2028, a volume that would turn Google’s in-house silicon program into one of the largest AI chip deployments in the market.
Google has been designing its own tensor processing units for roughly a decade, using them to run AI workloads inside its own infrastructure. A TPU is an AI accelerator built for matrix-heavy machine-learning jobs, the kind that sit behind model training and inference rather than general-purpose computing.
Fubon estimated that Nvidia supplied 8.2 million data center AI GPUs in 2026 and could reach 12.4 million units in 2028. If both estimates hold, Google’s planned TPU volume would be comparable to Nvidia’s 2028 AI GPU shipments, and the high end of Google’s range would exceed them.
How many Google TPUs could be built in 2028?
Fubon’s range is 12 million to 15 million TPU v9 processors in 2028. The firm said the TPU v9 design uses four compute dies, which would more than double Google’s capacity consumption in 2028 compared with 2027.
That four-die design matters because it increases the manufacturing and packaging burden. Multi-die accelerators rely on advanced packaging to connect compute chiplets at high bandwidth while keeping power and signal integrity under control. In practice, the package becomes part of the chip architecture, not an afterthought bolted on after tapeout.
Fubon said it does not yet have Google’s detailed manufacturing allocation. Even so, the firm argued that TSMC alone would likely struggle to support Google’s target, and that Intel Foundry supply would be needed by 2028.
Bloomberg reported in June 2026 that Intel had received orders to manufacture more than 3 million TPUs for Google after Google tested Intel’s advanced packaging technology for months. The Fubon note points to the same constraint: once a chiplet design is tied to a packaging method, moving between suppliers is not trivial. Intel’s EMIB and EMIB-T packaging and TSMC’s CoWoS-L are described as incompatible approaches, meaning the compute dies need to be designed with the chosen packaging flow in mind.
What would this mean for Nvidia?
Fubon’s claim does not mean Nvidia would stop growing. The same note projects Nvidia’s data center AI GPU shipments rising from 8.2 million in 2026 to 12.4 million in 2028, and the report says Nvidia’s AI GPUs are sold out. The risk for Nvidia is more strategic: Google’s TPUs run on a software stack outside Nvidia’s CUDA ecosystem, which remains Nvidia’s central advantage in AI compute.
If Google reaches the stated range while continuing to buy Nvidia hardware, it would become one of the world’s largest consumers of AI accelerators. The chips would feed Google’s own data center fleet, though Fubon’s note does not say how much capacity Google would keep for its services versus offering through cloud customers.
The performance comparison is still unresolved. Fubon’s note does not provide benchmarks for TPU v9 against Nvidia’s Rubin or Rubin Ultra platforms. Unit counts show manufacturing ambition and purchasing power, but they do not prove that Google’s 2028 accelerators will match Nvidia’s chips on training speed, inference efficiency, software support, or customer adoption.
This story draws on original reporting from Tom's Hardware.
