A reported kioxia sandisk 332-layer qlc NAND demonstration claims a striking 37 Gb/mm² areal density, but the supplied first-party record does not confirm that particular device. Tom’s Hardware reported that Kioxia and Sandisk showed the BiCS10 QLC part at the Future of Memory and Storage conference, with 332 active layers, an interface rated up to 4,800 MT/s and separate command address capability. The companies have officially described a different 332-layer BiCS generation 10 TLC product.
That distinction is doing real work here. The reported QLC device’s 37 Gb/mm² figure should be treated as a claim reported by Tom’s Hardware, rather than an independently established record. Kioxia and Sandisk have not supplied, in the available material, a matching announcement, a QLC die capacity or a commercial availability date. Tom’s Hardware says the QLC device is intended for high-capacity data-center SSDs, but its capacity was not disclosed.
What is the difference between the 37 Gb/mm² QLC claim and the 29 Gb/mm² TLC chip?
Kioxia’s June 2025 technical disclosure identifies the documented product as a 1Tb, 3b/cell TLC BiCS generation 10 chip. It has 332 stacked word lines, a density of 29 Gb/mm² and a 4.8Gb/s data-transfer rate, according to Kioxia. The reported 37 Gb/mm² QLC device and that disclosed 1Tb TLC chip are different devices; their density and capacity figures cannot be combined.
Layer count alone does not settle the density question. Kioxia attributes the TLC result to its taller stack and layout changes, including a floor plan that arranges four planes vertically to shrink bonding-pad and overhang area. In short, the useful measure is bits per unit of chip area, not a layer-count arms race with a ruler attached.
The shared technology has a few plumbing changes behind the speed claim. Sandisk says its CBA approach makes the CMOS logic wafer and the memory-cell-array wafer separately, then bonds them. SCA separates the command/address-input bus from the data-transfer bus so they can operate in parallel. Sandisk also describes PI-LTT as a NAND-interface technique meant to reduce I/O power consumption.
For the TLC technology previewed at ISSCC 2025, Sandisk and Kioxia said they expected a 33% NAND-interface-speed improvement over their eighth-generation flash then in mass production, reaching 4.8Gb/s. Sandisk reported 10% lower input I/O power and 34% lower output I/O power. Kioxia separately reported a 29% improvement in read-energy consumption for its TLC product. Those are company-reported technical results for the TLC product, not SSD-level benchmarks.
Which 332-layer products are actually sampling?
Kioxia said on July 30 that its CM10 enterprise SSDs use 332-layer generation 10 TLC flash and are sampling to select customers. The company lists capacities from 1.60TB to 61.44TB across form factors, while noting that the 2.5-inch model instead uses generation 8 TLC. Kioxia also warns that sample specifications can change before mass production.
That makes the current product status less glamorous but clearer: 332-layer TLC SSD samples are confirmed, while the reported high-density QLC device remains a separately reported demonstration with key details still missing.
This story draws on original reporting from Tom's Hardware.
