SMIC’s third-generation 7nm-class process, known as N+3, has reached a level of physical scaling that would have looked implausible for a Chinese foundry operating without EUV lithography. A teardown of Huawei’s Kirin 9030 smartphone chip by SemiAnalysis, with High Yield, found a minimum metal pitch of 32.5 nanometers and an estimated transistor density of about 113.4 million transistors per square millimeter.
That density is slightly above the 107.7 million transistors per square millimeter cited for TSMC’s N6 process, which uses multiple EUV layers. SMIC, by contrast, is reported to be using deep ultraviolet lithography with multi-patterning, including self-aligned quadruple patterning on the most constrained layers. That is a harder, messier route to fine features: the fab prints patterns in multiple steps and relies on alignment tricks rather than a single cleaner EUV exposure.
The result is a real manufacturing achievement. It is also not proof that SMIC has caught Intel or TSMC at the leading edge.
Density is only one scoreboard
SemiAnalysis said N+3’s 32.5-nanometer minimum metal pitch is tighter than the roughly 36-nanometer pitch used for many high-performance cells in Intel’s Panther Lake CPU. Intel 18A can support about 32-nanometer metal pitches, according to the same analysis, so the comparison is more awkward than a single number suggests.
The teardown did not disclose several measurements needed for a proper node-to-node comparison, including contacted gate pitch, standard cell height and fin pitch. Those numbers matter because a process is a stack of trade-offs, not a vanity contest over one layer. A dense metal layer can help shrink a design, but it does not by itself determine switching speed, leakage, routing congestion, yield or power delivery.
SemiAnalysis attributed SMIC’s density gains to aggressive design-technology co-optimization and layout choices that may include reduced fin counts, contacts placed directly over active gates and tighter cell isolation. Those techniques can pack more transistors into a given area. They can also make the process harder to manufacture, raise costs, narrow design flexibility and increase yield risk.
The Kirin 9030 still trails current flagship chips
The Kirin 9030 does not appear to translate that density into top-tier phone performance. SemiAnalysis characterized the chip as delivering performance in the range of flagship application processors from about three years ago, with a large energy-efficiency gap versus current designs from Apple, Qualcomm, MediaTek and Samsung.
According to the analysis, Huawei’s fastest CPU core is roughly in the Cortex-X2 class for instructions per clock. SemiAnalysis also said Apple’s much smaller efficiency cores beat it in integer workloads while using considerably less power.
That gap is why the Intel 18A comparison needs restraint. Intel’s 18A process uses gate-all-around transistors and backside power delivery, two changes aimed at improving control of current flow and reducing power delivery bottlenecks. SemiAnalysis said 18A offers higher transistor density and substantially better performance efficiency than SMIC’s N+3, despite the headline-grabbing metal pitch comparison.
SemiAnalysis concluded that export controls have slowed China’s chipmaking progress rather than stopped it. The firm said SMIC could keep pushing density through tighter metal layers, shorter standard cells, smaller gate pitches and, eventually, backside power delivery. Its projection was that a future N+4 process could approach TSMC N5-class density, while an N+5 process with backside power might reach Intel 18A-class density.
Those are forecasts, not shipping silicon. For now, the Kirin 9030 shows SMIC can squeeze more density out of DUV than many expected. It also shows why density alone is a bad proxy for a competitive leading-edge process.
This story draws on original reporting from Tom's Hardware.
