TYLsemi chiplet funding is now public: the new semiconductor company said it has raised $43 million in early-stage capital as it pitches a cheaper route to custom processors for AI infrastructure. The company, pronounced “Tile Semi,” is not trying to be only another custom ASIC contractor. Its pitch is to combine customer-owned compute silicon with reusable chiplets for functions such as connectivity and power delivery.
TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, chip-industry veterans whose prior employers include Alphawave, SiFive, Cadence and Rambus. Gupta, TYLsemi’s chief executive, told Tom’s Hardware Premium that the timing is better now because advanced packaging has moved into volume production, UCIe die-to-die standards are reaching deployments, and customers want less fragile supply chains.
What is TYLsemi building?
TYLsemi is building “foundation chiplets,” reusable dies that handle common processor functions so customers can spend more of their engineering budget on the compute block that makes their chip different. In a chiplet design, several smaller dies are packaged together as one system-in-package, instead of forcing every function into one very large piece of silicon.
The first product family, TYL.IO, is aimed at connectivity. Gupta said the initial I/O chiplet will provide 32 lanes of PCIe Gen 7 and CXL, linked to the host compute die over UCIe. A later member of the family is planned for rack-scale XPU connections using high-speed SerDes, with about 72 lanes and roughly 14 TB/s of bandwidth, according to Gupta. TYLsemi also lists an electrical interface chiplet roadmap for co-packaged optical connectivity.
The company is also planning TYL.Power, a 16 nm in-package integrated voltage regulator chiplet with embedded passives, and TYL.Mem, a memory-connectivity family whose architecture and specifications have not been disclosed. TYLsemi says samples of TYL.IO and TYL.Power will be available to qualified customers in 2027, with first I/O samples expected in the second half of that year.
How does TYLsemi say this saves money?
TYLsemi’s argument is yield and process discipline. Large AI and HPC accelerators can approach reticle-sized dies, and Gupta told Tom’s Hardware Premium that dies in the 500 mm² to 600 mm² range make yield and timing closure harder. The company says customers could keep advanced logic on a leading-edge node while moving I/O and power functions to older, cheaper processes that fit those functions better.
The company offered an illustrative estimate, not a manufacturing quote: at 100,000 devices, it says a monolithic 700 mm² 3 nm-class chip could cost $350 million in total ownership, while a package using a 500 mm² compute die plus four 100 mm² I/O chiplets on an N-1 process could cost $150 million. TYLsemi also estimates the monolithic part at $3,000 per unit versus about $600 for the system-in-package. Those numbers are company claims and depend on design, process, packaging and volume.
TYLsemi also wants to sell services under TYL.Forge. Customers could bring mature RTL, a netlist, an architecture concept or an existing compute die. TYLsemi says it would handle implementation, integration with its chiplets, tape-out, packaging, assembly, testing, qualification and volume production. Gupta said the company does not intend to invent the customer’s core compute architecture.
Gupta said TYLsemi is initially focused on TSMC’s ecosystem, while leaving open future use of other packaging supply chains, including Intel, ASE, Amkor or others. The company expects customer processors using its approach to reach the market around 2029 to 2030.
This story draws on original reporting from Tom's Hardware.
