AMD Epyc 9996 benchmarks are now public, and the company is using its first detailed Zen 6 server CPU disclosure to pick fights with Intel’s Xeon 6 and Nvidia’s Vera. AMD says the 256-core, 512-thread Epyc 9996 is the first part in a wider Venice server lineup, with more specialized chips planned across different sockets and workload targets.
AMD corporate vice president Ravi Kuppuswany described Venice as a portfolio, with purpose-built variants rather than one generic server part. The main Venice family uses the SP7 socket and scales to 256 cores, 512 threads, 16-channel memory, 1.6 TB/s of memory bandwidth with fast MRDIMMs, and 128 PCIe 6 lanes in a one-socket system. Two-socket systems get 160 PCIe 6 lanes, according to AMD.
What is AMD Epyc 9996 Venice?
The Epyc 9996 is AMD’s dense Zen 6c version of Venice, which is how AMD reaches 256 cores in one socket. Standard Zen 6 Venice parts top out at 128 cores, while high-frequency variants stop at 96 cores and can reach 5 GHz, according to AMD.
AMD said Zen 6 is built on TSMC’s N2 process. The dense design uses 32-core CCDs and two I/O dies. The 256-core configuration carries 1,024 MB of L3 cache, with 128 MB per CCD and 4 MB per core. AMD said this cache is not stacked; stacked cache is reserved for Venice-X.
The memory system is a major part of AMD’s pitch. Venice SP7 supports 16 memory channels, MRDIMMs at 12,800 MT/s, or DDR5 RDIMMs at 8,000 MT/s. AMD claims 1.6 TB/s of per-socket bandwidth, compared with Nvidia’s claimed 1.2 TB/s for Vera and 576 GB/s for AMD’s prior Turin platform. Intel has enabled 8,000 MT/s RDIMMs on some Granite Rapids and Clearwater Forest chips, and says 8,800 MT/s MRDIMM support is coming in the first quarter of 2027.
How AMD says Venice compares with Xeon and Vera
AMD did not provide a full SKU list, so the benchmark picture is still selective. The company compared the Epyc 9996 with Intel’s Xeon 6980P, AWS Graviton5, and AMD’s own Epyc 9755 and 9965 across several tests centered on agentic AI and adjacent server work.
- In an NGINX web server test using the WRK load generator, AMD reported 28,789,170 maximum requests per second for Epyc 9996, versus 10,162,179 for Xeon 6980P and 24,320,476 for Epyc 9965.
- In the TPCx-AI benchmark, AMD reported 5,982.91 AI use cases per minute for Epyc 9996, compared with 1,750.36 for Xeon 6980P and 3,458.79 for Epyc 9965. AMD characterizes that as 3.4x over Intel and 1.7x over Turin.
- Using Meta’s open-source FAISS library on the siftm1 dataset, AMD reported 751,453 queries per second for Epyc 9996, compared with 316,069 for Xeon 6980P and 472,079 for Epyc 9965.
- Across TPC-H, TPC-C, Redis, and related enterprise tests, AMD reported a geomean throughput of 6,054,748 for Epyc 9996, versus 2,284,701 for Xeon 6980P.
For Nvidia Vera, AMD compared against Nvidia’s published SPEC CPU 2026 results and said it used the same GNU 15.2 compiler. AMD claims the 256-core dense Venice chip delivers 2.2x the SPECrate integer throughput of Vera, while a 96-core high-frequency Venice chip delivers 1.2x per-core performance. AMD said both Venice configurations used a 600W TDP.
AMD’s roadmap also includes smaller SP8 Venice chips, planned for the first half of next year, ranging from eight to 128 cores with eight-channel memory and 128 PCIe 6 lanes. Venice-X is expected in the second half of 2027 with 96 cores, up to 1,152 MB of stacked L3 cache, and a 5.15 GHz boost clock. Verano, aimed at AI host-node duty, is planned for the second half of next year with up to 72 cores, 5 GHz peak clocks, and 24-channel LPDDR5X memory using SOCAMM2 modules.
This story draws on original reporting from Tom's Hardware.
