AMD said its AMD Venice-X CPU will launch in the second half of 2027, giving high-performance computing buyers a first concrete look at the cache-heavy Zen 6 server chip. The company disclosed the part Thursday at its Advancing AI event, alongside the broader Venice data-center lineup.
Venice-X uses the same Zen 6 microarchitecture as Venice SP7, which AMD says is already in production. The X variant trades the very highest core counts for a much larger cache allocation per core: AMD lists 96 cores, up to 5.15 GHz boost clocks and 1152 MB of L3 cache using its 3D V-Cache stacking technology.
3D V-Cache is AMD’s method for placing additional L3 cache on the processor package rather than relying only on the cache built into the main compute die. For workloads that repeatedly touch large working sets, more nearby cache can reduce trips out to main memory, although AMD did not publish Venice-X performance estimates.
When does AMD Venice-X launch?
AMD says Venice-X is scheduled for the second half of 2027. That puts it well after the current Venice production announcement, and it also means most of the claims remain product-roadmap disclosures rather than independently tested specifications.
The design echoes earlier AMD Epyc X-series chips such as Milan-X and Genoa-X, which paired server CPUs with expanded L3 cache. AMD did not release a Turin-X part, and until this event it had not provided firm public details for Venice-X.
Compared with Genoa-X, AMD is holding the core count and cache total at familiar headline levels while raising the stated clock ceiling. The 96-core Epyc 9684X reaches up to 3.7 GHz, while AMD says Venice-X can boost as high as 5.15 GHz. That number is a company specification, not a measured benchmark.
Venice-X also inherits the memory platform changes AMD is putting across much of the Venice range. The chip supports 16-channel memory, with standard DDR5 RDIMMs running up to 8,000 MT/s or MRDIMMs up to 12,800 MT/s. AMD says that configuration can provide as much as 1.6 TB/s of aggregate memory bandwidth.
AMD frames that memory system as a large step over Turin, mostly because MRDIMMs enable higher transfer speeds. Venice-X keeps the same SP7 socket as the main Venice family. Other Zen 6 server variants, including Verano, are slated to use SP8 instead.
The cache math is the point of the X model. Standard Venice chips can include up to 1024 MB of L3 cache, according to AMD, but that cache is spread across as many as 256 cores. Venice-X offers a slightly larger total L3 pool to far fewer cores, giving each core a much larger share.
AMD identified Venice-X as one of four Zen 6 data-center variants and said it is aimed mainly at HPC workloads. The company did not disclose pricing, detailed model names, power limits, or application-level performance numbers.
This story draws on original reporting from Tom's Hardware.
