Tom's Hardware reports that IBM used Hot Chips 2026 to disclose an IBM dual-ISA processor for a future mainframe generation, alongside a new AI accelerator. The consequential bit is architectural: IBM says a single CPU core can run either its z/Architecture instructions or Arm's AArch64 instructions, rather than placing separate Arm and mainframe cores in the same package.
That could give IBM Z customers a route to run software built for the Arm ecosystem without moving that work to a separate Arm server fleet. IBM says the core can change its active instruction set dynamically within nanoseconds. The company’s first-of-its-kind claim remains its own, and the available reporting does not include independent performance testing or a confirmed product launch date.
How does IBM's dual-ISA processor work?
An instruction set architecture, or ISA, is the hardware contract that defines the instructions compiled software can execute. Arm and other instruction set families generally require software to be compiled for their particular machine model. IBM’s reported approach puts hardware support for both z/Architecture and AArch64 inside each core, so this is more than emulation or a heterogeneous chip design.
According to IBM’s presentation as described by Tom’s Hardware, the chip implements AArch64 v9.3 in hardware, including Scalable Vector Extension support, and recognizes 2,792 AArch64 instructions. IBM uses Linux Kernel-based Virtual Machine, or KVM, for the AArch64 path; ordinary z/Architecture instructions bypass KVM. IBM also says Arm applications can run without modification and Arm virtual machines can operate as native Arm systems. Those are compatibility claims from IBM, not yet independently verified results.
The processor is reported to have 11 high-performance cores built on a 2nm process, with a disclosed 5.7 GHz base frequency. It supports simultaneous multithreading under both ISAs, according to the report. Other listed hardware includes 36 MB of private L2 cache, 432 MB of virtual L3 cache, 3.5 GB of virtual L4 cache, an on-chip data processing unit, and accelerators for AI, compression, and cryptography.
What changes from Telum II?
Tom’s Hardware characterizes IBM’s 2024 Telum II as an eight-core processor running at up to 5.5 GHz. The reported new design keeps 36 MB of private L2 cache while increasing the cited virtual L3 and L4 capacities. Core count and clock figures do not establish a like-for-like performance gain, particularly without workload benchmarks.
IBM also previewed a separate next-generation AI accelerator. The company says it has 16 cores, supports newer AI number formats including FP4 and MXFP4, and replaces LPDDR5 memory with 96 GB of HBM3e. IBM claims up to 4 TB/s of bandwidth, which Tom’s Hardware describes as 20 times the LPDDR5 bandwidth IBM can deliver. The report does not establish a shipping date, final product name, or whether the CPU will appear in a system called z18.
This story draws on original reporting from Tom's Hardware.
