Intel Xeon 7 Diamond Rapids is Intel’s next server-processor design, and the company used Hot Chips 2026 to disclose a package built around up to 256 cores, 1.28GB of last-level cache, 16 memory channels and 128 lanes for PCIe 6.0 and CXL 3.0. Intel is pitching the chip for enterprise-scale agentic-AI workloads, though the presentation supplied no benchmark results to test that pitch.
Intel’s announcement calls those “new cores.” Tom’s Hardware reports they are P-cores, that the family is due in data centers in 2027, and that it adds AVX 10.2. Those details were not confirmed in Intel’s supplied announcement, so they remain reported rather than company-specified here.
How does Intel Xeon 7 Diamond Rapids reach 256 cores?
The disclosed architecture is a tiled one. Intel calls its compute modules Compute Building Blocks, while the central fabric hubs handle memory and I/O. Tom’s Hardware reports that the maximum configuration has four Compute Building Blocks, each carrying four core chiplets with up to 16 cores apiece. The arithmetic is refreshingly uncomplicated: four blocks times four chiplets times 16 cores equals 256.
Each core chiplet sits over a base tile holding shared last-level cache. Tom’s Hardware reports that Intel uses Foveros Direct 3D to bond those compute and base tiles vertically. That is packaging, not the same thing as semiconductor fabrication, the wafer-making process that creates the individual dies.
The wider package uses a different link. Intel identifies UCIe-S as part of the SoC construction, and Tom’s Hardware reports substrate-copper UCIe-S connections between the compute blocks and two fabric hubs. The same report says Intel has not used its Embedded Multi-die Interconnect Bridge, or EMIB, for this design. In other words, Foveros handles the vertical stack within a compute block; the reported UCIe-S links connect that block to the centralized hubs.
What memory and I/O does Diamond Rapids support?
Intel lists 16 memory channels running at up to 12,800 MT/s, along with 128 lanes of PCIe Gen6 and CXL 3.0. Tom’s Hardware adds that the memory options include DDR5 up to 8,000 MT/s and MRDIMMs up to 12,800 MT/s. It also reports that the 128-lane flexible I/O budget can be assigned among PCIe 6.0, CXL 3.0 and UPI 3, rather than being a promise of 128 lanes for each interface.
Intel says the compute chiplets use its enhanced 18A-P process, while the architecture combines a unified memory fabric with flexible I/O. Tom’s Hardware reports the fully scaled SoC contains 16 18A-P core chiplets, four Intel 3-T base tiles and two Intel 3 fabric hubs. Intel also highlights APX and enhanced AMX, and Tom’s Hardware reports on-chip QuickAssist Technology and In-Memory Analytics Accelerator blocks.
The important omissions are just as clear. Intel did not detail the underlying Panther Cove core architecture at Hot Chips, according to Tom’s Hardware. Clock speeds, power figures, SKU layouts, pricing and measured performance are also absent from the supplied material. The package design is now substantially clearer; the per-core story is not.
This story draws on original reporting from Tom's Hardware.
