The latest Nova Lake cache leak revises the reported native L3 totals for two Intel configurations with a reduced Efficient-core cluster. Tipster Jaykihn now claims an 8P+12E+4 part would carry 36MB, rather than the previously reported 33MB, while a 4P+4E+4 part would carry 18MB rather than 15MB. Intel has not announced or confirmed these processors or their specifications.
The notation in the reported SKU chart is P+E+LP-E: Performance cores, Efficient cores and Low Power Efficient cores. The trailing +4 therefore is not another four standard E-cores, a detail that tends to get lost once leak charts start doing the rounds.
Which Nova Lake CPUs may keep their full L3 cache?
According to Tom’s Hardware’s report on Jaykihn’s update, an 8P+12E+4 configuration would retain the same 36MB native L3 allocation listed for the 8P+16E+4 version. Likewise, the report puts both 4P+4E+4 and 4P+8E+4 at 18MB of native L3 cache.
- 8P+12E+4: reported at 36MB native L3, up from an earlier 33MB prediction.
- 8P+16E+4: also reported at 36MB native L3.
- 4P+4E+4: reported at 18MB native L3, up from an earlier 15MB prediction.
- 4P+8E+4: also reported at 18MB native L3.
The claimed pattern is narrower than “disabled E-cores do not affect cache.” It says a chip with one cut-down E-core cluster can, in some cases, retain the cache setup of its non-cut-down counterpart. That is a claim about how Intel might divide its future product lineup, not proof of performance. There are no Nova Lake benchmarks, clocks, prices or final product names in the evidence here.
There is also an exception, and the reporting around it is annoyingly untidy. Tom’s Hardware’s SKU table lists the 6P+12E+4 configuration at 27MB of L3 before and after the update, meaning it does not receive an analogous increase. But the embedded Jaykihn post says that configuration remains at 30MB. The shared conclusion is that the 6P+12E+4 part is outside the newly claimed retention rule; its precise reported total is inconsistent within the same report.
Does this change Nova Lake’s reported big last-level cache?
No. The revised figures concern native L3 cache. The report separately lists rumored big last-level cache, or bLLC, allocations for certain SKUs, including 132MB for 8P+12E+4 and 108MB for 6P+12E+4. Those bLLC figures were not revised by this update and remain unconfirmed. A July HotHardware report also described bLLC as a rumored feature that could appear at different capacities across Nova Lake tiers.
Tom’s Hardware says the same alleged cache treatment extends to the reported Nova Lake-HX mobile lineup. That remains a leak claim, not an Intel specification. The report has floated a possible CES 2027 announcement, but Intel has announced no Nova Lake launch date in the material reviewed.
This story draws on original reporting from Tom's Hardware.
