Nvidia has published its first benchmark figures for Vera, its Arm-compatible server CPU built around custom Olympus cores, and ServeTheHome is already poking at the comparison chart with a calculator. That is useful because buyers reading vendor CPU slides are usually being shown the best angle, not the whole machine room.
Patrick Kennedy of ServeTheHome said Nvidia’s Vera whitepaper compares the new chip against AMD’s current Epyc Turin generation, including the 128-core Epyc 9755. Kennedy said Vera looks like an interesting part and expects Nvidia to sell many of them, while arguing that Nvidia’s framing uses choices that make the headline gaps look larger than a more normalized comparison would.
The main issue is denominator math. Nvidia cites Vera at up to 1.2TB/s of memory bandwidth using LPDDR5X-9600, compared with roughly 0.6TB/s for AMD’s 2024-era Epyc 9755 with 12 channels of DDR5-6400, according to ServeTheHome. That raw bandwidth gap is real in the figures discussed. The per-core chart, however, widens the visual hit: Nvidia divides its bandwidth across 88 Vera cores, while AMD’s figure is divided across 128 Epyc cores.
ServeTheHome said Nvidia’s whitepaper shows 12.7GB/s per core for Vera against 3.1GB/s per core for the Epyc 9755. Kennedy argues that AMD’s 96-core Epyc 9655 would be a cleaner current-generation comparison because its core count is closer to Vera’s 88 cores. Using a 128-core AMD chip makes AMD’s per-core number smaller by construction.
Memory gains are also generational
Some of the comparison is less about Nvidia versus AMD and more about when each memory subsystem ships. ServeTheHome notes that larger memory-channel counts and faster memory standards routinely produce big chart jumps. Kennedy compares the pattern to AMD’s own move from Milan, with eight channels of DDR4-3200, to Genoa, with 12 channels of DDR5-4800.
AMD has said its next-generation Venice CPU will reach 1.6TB/s of memory bandwidth, and ServeTheHome says it has shown 16-channel Venice systems. Kennedy said he remained under embargo for Venice details, so his analysis stays anchored to Turin. That caveat matters: Nvidia is comparing a 2026 Vera part with AMD’s outgoing server CPU generation, according to ServeTheHome.
Latency charts need workload context
Nvidia’s whitepaper also includes a core-to-core latency heat map, where AMD’s chiplet-based Epyc design shows higher latency outside certain core complexes and chiplets, while Vera’s topology appears more uniform, according to ServeTheHome. Kennedy says the direction is fair: chiplet hops add latency.
He questions how much that hurts the workloads Vera is being pitched at. ServeTheHome says agentic workloads often run inside virtual machines, containers, or sandboxes using one to four cores. Those can fit inside a single AMD core complex if the operating system scheduler places them sensibly. In that case, the workload stays in the low-latency part of AMD’s topology.
Vera still has a practical advantage if a scheduler scatters a small workload across distant cores, Kennedy wrote. A monolithic design gives administrators less topology pain to trip over. The wrinkle is that Nvidia’s 88-core Vera cannot match a 128-core Epyc socket on core count without moving beyond one socket. ServeTheHome says cores 89 through 128 in such a Vera comparison would have to come from a second socket, where socket-to-socket links are expected to add latency and jitter.
The short version from ServeTheHome: Nvidia’s Vera numbers are meaningful, but the charts are doing vendor-chart things. Memory bandwidth, core count, chip topology, and the chosen AMD comparison part all change the story before anyone gets to real deployment behavior.
This story draws on original reporting from ServeTheHome.
