Nvidia has put more meat on the bones of Vera, its upcoming server CPU, releasing a full architectural whitepaper for the chip alongside new material on Rubin GPUs and the NVLink fabric tying the platform together.
The useful bit for server buyers is Vera. According to Nvidia’s disclosures, the chip moves beyond Grace’s Arm Neoverse V2 cores to Olympus, a Nvidia-designed CPU core. ServeTheHome reports that Nvidia is also publishing its first SPEC CPU 2026 results for Vera, giving an early, company-supplied view of performance. The reported readout is mixed: it shows where Nvidia spent its transistor budget, while leaving open questions about broader CPU competitiveness.
Vera is not being positioned only as the host processor glued to a GPU box, the role Grace largely served. Nvidia wants the CPU to fit a wider range of servers and to make customers less tempted to pair Rubin GPUs with processors from Intel, AMD, or other Arm server vendors. That is a harder fight than selling accelerators into AI clusters, since the server CPU field already has mature incumbents and plenty of Arm competition.
What Nvidia disclosed about Vera
Compared with Grace, Vera raises several headline specifications. Nvidia lists 88 Olympus cores and 176 threads using spatial multithreading, up from Grace’s 72 cores and 72 threads. L2 cache doubles to 2MB per core, while the shared L3 cache rises to 164MB from 114MB.
Memory is also a central part of the pitch. Nvidia says Vera supports up to 1.2TB/s of LPDDR5X bandwidth and up to 1.5TB of memory capacity. Grace topped out at up to 512GB/s and 480GB, respectively. NVLink-C2C bandwidth doubles to 1.8TB/s, and Vera moves to PCIe Gen6 and CXL 3.1. The thermal design power range grows as well, from Grace’s 250W to 250W to 450W for Vera.
The core itself looks like a wide, contemporary high-performance CPU design rather than an architectural science project. Nvidia had already discussed a neural branch predictor that can produce two branch predictions per cycle. The new disclosures add that Olympus can fetch up to 16 instructions, each 64 bits, into a decode queue holding 48 instructions. From there, the core can deliver up to 10 fused instructions into a 10-wide decoder.
Olympus goes wide
Nvidia also confirmed the L1 cache layout: each core has a 64KB, 4-way instruction cache and a 96KB, 6-way data cache. ServeTheHome notes that the instruction cache is twice the size of AMD Zen 5’s L1 instruction cache and matches Intel’s Cougar Cove figure.
In the out-of-order portion of the core, Nvidia says Olympus can rename up to 10 micro-ops per cycle. The company has not disclosed the reorder buffer size or register file sizes, which are the kind of details CPU people tend to ask for first, because marketing diagrams rarely run code.
Nvidia says Olympus uses memory renaming, value prediction, and move elimination to find more instruction-level parallelism. Memory renaming lets the processor break some dependencies around memory addresses, while value prediction speculates on repeated values and checks the result later.
The backend is large. Nvidia’s whitepaper describes 18 execution pipes per core: eight for integer arithmetic and branching, six for vector and floating-point work, four for loads, and two for stores. The pipes are arranged in pairs, which Nvidia ties to its spatial multithreading design. All eight integer pipes handle simple operations, while two also support complex operations such as multiply, divide, CRC, and bit shifting.
The SPEC CPU 2026 numbers are still early and vendor-published. Treat them as a starting point, not a verdict. What Nvidia has confirmed is more concrete: Vera is a serious attempt to build a broader server CPU, and Olympus is much wider than a checkbox host core for an AI appliance.
This story draws on original reporting from ServeTheHome.
