TSMC says its next major chipmaking process, A14, has improved quickly over the past quarter, a useful signal for customers planning expensive smartphone and AI processors around a node that is still years from production.
On the company’s earnings call this week, chief executive C.C. Wei said an internal product-like test vehicle for A14 had reached close to 90% of target device performance and close to 90% yield on a 256Mb SRAM test chip. TSMC classifies A14 as a 1.4nm-class process and expects it to enter mass production in the second half of 2028.
The new figures are up from the numbers TSMC disclosed in April, when it said A14 had achieved more than 85% of target transistor performance and more than 80% yield on the same size SRAM structure. That points to roughly five percentage points of performance progress and almost 10 percentage points of SRAM yield improvement in about three months.
Why the SRAM number matters, and what it does not prove
SRAM yield is a standard early health check for a process because memory arrays are dense, repetitive structures that expose defect density and process-uniformity problems. It is not the same thing as proving a commercial CPU, GPU, or AI accelerator will yield well. Large processors add logic, analog blocks, interconnect complexity, timing constraints, and many more ways to make a very expensive rectangle of silicon misbehave.
Still, the comparison with TSMC’s N2 process is favorable for A14. TSMC’s N2 had reached more than 80% of target device performance and more than 50% yield on a 256Mb SRAM test chip in April 2023. By April 2024, N2 had moved above 90% performance and above 80% SRAM yield. The timelines are not perfectly comparable, but A14 appears to be further along than N2 was at a similar development point.
One reason may be less mysterious than the usual node-name fog. N2 is TSMC’s first process built around gate-all-around nanosheet transistors. A14 uses the company’s second generation of that transistor structure, so TSMC can apply lessons from N2’s design work, process tuning, and manufacturing ramp rather than learning the device architecture from zero.
Customers are already lining up designs
Wei also told analysts and investors that TSMC is seeing strong engagement for A14 from both smartphone and high-performance computing and AI customers. He said customer tape-out activity is underway and ahead of schedule. A tape-out is the point where a chip design is handed off for manufacturing, or at least for the next serious step toward it. In other words, these are not just slide-deck commitments.
A14 combines TSMC’s second-generation gate-all-around nanosheet transistors with a new standard-cell architecture. Compared with N2, TSMC projects A14 will deliver 10% to 15% higher performance at the same power and transistor count, or 25% to 30% lower power at the same frequency and complexity. The company also expects around 20% higher transistor density for mixed designs and 23% for logic.
The node will not include TSMC’s Super Power Rail backside power delivery, according to the company’s roadmap details cited in the discussion. Even so, Wei said A14 is drawing interest beyond phone chips, including AI and high-performance computing designs. That suggests customers may see enough benefit in the transistor and density gains to move before backside power arrives on a later process.
This story draws on original reporting from Tom's Hardware.
