Samsung zHBM AI memory is the company’s proposed answer to the increasingly awkward distance between AI processors and the data they need. At the Future of Memory and Storage conference in Santa Clara, California, on August 5, Samsung Electronics previewed zHBM and zNAND-O concept models and introduced its V10 BV-NAND flash architecture. The three announcements share a 3D-integration theme, though Samsung explicitly ties wafer bonding to zHBM and BV-NAND, not zNAND-O.
That distinction matters. Samsung has not announced availability, pricing, production yields, customer deployments or independent benchmarks for these technologies. Two are concepts, and the biggest figures on the slide deck are company expectations rather than measured product results.
How does Samsung zHBM differ from conventional HBM?
Conventional high-bandwidth memory, or HBM, sits beside an AI processor in the package. Samsung’s zHBM concept moves the HBM stack directly above the AI accelerator. The intended result is a shorter processor-to-memory path, which Samsung says is designed to increase bandwidth and improve power efficiency for AI training and inference.
Samsung says a next-generation interface using zHBM could provide roughly eight times the “performance” of HBM5. It also says next-generation wafer bonding could allow more than 10 times HBM5’s memory density, three times its energy efficiency and thermal resistance reduced by more than half. Those are prospective claims, and Samsung has not defined what its eight-times performance measure covers. As Tom’s Hardware noted, it is unclear whether the comparison refers to bandwidth, application performance or another metric.
Samsung says customers could add their own intellectual property to an interlayer between the memory and accelerator. That suggests zHBM is being pitched as a tailored package architecture rather than a drop-in, standardized memory part.
What are zNAND-O and V10 BV-NAND?
zNAND-O addresses storage rather than working memory. Samsung describes it as an in-development, V-NAND-based high-performance NAND design planned in four- and eight-layer versions. The company says it is aimed at edge AI, where processing happens closer to devices and data sources, and cites space efficiency, higher I/O performance and low latency as its goals. Edge computing moves processing nearer to where data is created, rather than requiring every task to go to a distant cloud facility.
V10 BV-NAND is the more concrete flash announcement. Samsung says its Bonding V-NAND architecture exceeds 400 layers and uses wafer bonding to stack memory cells. The company claims about 58% higher memory density than its V9 generation, plus better read, write and I/O performance, though it did not publish numerical results for those speed claims.
For readers sorting memory from storage: HBM supplies fast, temporary data access near a processor, while NAND retains data when power is off. Samsung is trying to alter both parts of that system, but the company has shown an architectural direction, not a completed AI-data-center product catalog.
This story draws on original reporting from Tom's Hardware.
